A Space- and Energy- Efficient Code Compression/Decompression Technique for Coarse-Grained Reconfigurable Architecture

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This paper introduces a code compression method to reduce the area and energy overhead of the configuration memory for coarse-grained reconfigurable architectures (CGRA). CGRA processors consist of an array of heterogeneous processing elements, data memory, register files, and constant units, which are connected through an interconnection network composed of multiplexers, latches, and wires to route data from producers and consumers. CGRA processors are operated based on a static data-flow graph (DFG) and store the execution plan in the configuration memory in advance. Based on this plan, the hardware entities are reconfigured for each cycle. As it stores the configuration for the entire hardware entities, the configuration memory occupies a significant amount of the entire chip area; the line width is typically more than 1000 bits and several hundred lines are required for small applications. The energy and memory consumption of the configuration memory is the main bottleneck of the CGRA processors. In this paper, we propose a code compression that removes consecutive duplicated lines in the configuration memory at compile time. In order to improve compressibility, we also propose optimizations that increase duplication by adding dummy instructions and partitioning the configuration memory. Our compression technique achieves a memory reduction of over 40% on over 190 loop kernels from different application domains.