Code Compression Technique Based on Flexible Bin-Packing Algorithm

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In this work, we present an improvement of our previous configuration memory compression technique. As the industry requires more flexibility to adapt the fast-changing application grows, coarse-grained reconfigurable architectures (CGRA) are in the spotlight. However, the area and power overhead of the configuration memory to configure the actions for entire hardware entities for each cycle are significant and hinder a broader deployment of CGRA chips. In our previous work, we have presented an efficient and lightweight compression technique of the configuration memory by removing consecutive duplicated lines. To generate compression-friendly code, we apply spatial and temporal optimization in the compiler backend. Here, we suggest an advanced compression technique based on a binpacking heuristics. The proposed technique is extremely flexible since the technique can predetermine the number of partitions and bitwidth of each partition. In addition, the compressibility of code is improved by applying a more sophisticated temporal optimization. Experiments with 247 kernels from various applications on the commercially used Samsung Reconfigurable Processor (SRP) show a memory reduction of over 75%, on average for individual loops. The compression of unseen code also achieves satisfactory reduction of 45% on average. Compared to previous work, we improve the compressibility by about 10 to 20% for all the benchmark domains.